Req ID:
JR94144 Senior Member of Technical Staff / Member of Technical Staff, DRAM Design Engineer, Next-generation HBM Architecture
Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Interested in changing the landscape of artificial intelligence workloads? Join our team where we are building next-generation, high-bandwidth memory products. In Micron's High Bandwidth Memory Architecture organization, we partner closely with customers to deliver memory solutions purpose-built for emerging AI systems and applications.
As a Senior Member of Technical Staff or Member of Technical Staff, DRAM Design Engineer in the next-generation HBM Architecture team, you will drive the architecture and optimization 3D-stacked, high-performance memories. Apply your knowledge to optimize DRAM designs and architectures for maximum performance, power, and area (PPA). This role is ideal for experienced DRAM designers who will identify, architect, design, and simulate next-generation architectures and memory features in collaboration with experts in stack architecture, memory systems architecture, and SoC microarchitecture.
Responsibilities:
- Identify and develop novel DRAM circuit architectures that anticipate next-generation AI workload requirements, to unlock improvements in bandwidth and energy efficiency.
- Collaborate with peers to identify the highest-leverage DRAM circuit bottlenecks and define architectural hypotheses.
- Validate architectural hypotheses through schematic-level circuit design, SPICE simulation, and tradeoff analysis, establishing PPA feasibility.
- Partner with layout designers to conduct floorplanning studies.
- Collaboratively define and optimize design-for-test, design-for-yield implementation.
- Compose and maintain clear specifications and architecture documentation.
Minimum Qualifications:
- Strong mixed signal design experience, including experience with custom analog and synthesis flows.
- DRAM circuit design experience in one or more of the following focus areas: cell arrays, sense amplifiers, row/column decoders, periphery, IO, and/or power distribution.
- Engineering experience with SPICE-based tools (e.g., FineSim, HSPICE).
- Strong communication skills with an ability to influence others through deeply technical, data‑driven analysis.
Preferred Qualification:
- Experience with HBM or other novel stacked memory architectures.
- Experience in one or more scripting languages (e.g., Python, Perl) and hardware description language (e.g., Verilog).
- Strong knowledge of semiconductor device physics.
- A Masters or PhD in Computer Science, Computer Engineering, Electrical Engineering, or equivalent experience.
- 8+ years of proven experience delivering DRAM-based memory designs.
Job Profile(s):
Systems Design Engineering SMTS
Relocation Level: TBD
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